1. Field of the Invention
The present invention relates to an LSI (Large Scale Integration) package and an internal connecting method used therefor.
2. Description of the Related Art
Currently, in the field of semiconductor packages, packages having new types of shapes have been developed one after another, in order to comply with requests such as minimizing and lightening, accelerating, and enhancing functions, for electronic apparatuses such as computers. As a result, a variety of packages presently exist.
In the typical structure of the packages, a bare chip which is provided on a die pad is connected with leads for achieving an electrical connection with outer circuits by bonding wires. Furthermore, on the die pad, the bare chip and channels which include the leads are covered by a package mold.
LSI packages having such structures are used by being mounted on printed-circuit boards of various electronic apparatuses. The LSI packages as described above are disclosed in Japanese Unexamined Patent Application, First Publication Nos. Hei 5-114776 and Hei 8-279590 and the like.
In a conventional bare chip, the bare chip is connected by providing solder bumps on the bare chip and soldering the bumps to a substrate or a film which is called an interposer. However, it is difficult to form very small solder bumps.
The object of the present invention is to solve the above problem, and to provide an LSI package without employing steps for forming solder bumps on the bare chip and soldering to the interposer, and an internal connecting method used therefor.
An LSI package of the present invention has a substrate in which a bare chip is mounted, wherein a build-up method is used for forming wiring patterns which connect input/output terminals of the bare chip and outer input/output terminals of the substrate.
Furthermore, the internal connecting method for an LSI package of the present invention is an internal connecting method for an LSI package having a substrate in which a bare chip is mounted. The method includes a step for forming wiring patterns which connect input/output terminals of the bare chip and outer input/output terminals of the substrate by a build-up method.
That is, the LSI package of the present invention is characterized by employing the wiring patterns formed by the build-up method as a means for mounting the bare chip and for the internal connecting thereof, instead of conventional bump connections.
In the present invention, since the connection between the bare chip and the interposer is accomplished by the build-up method instead of bump connections, the connection can be made without using solder between the very small solder bumps and the interposer. Consequently, it is unnecessary to employ the steps for forming the solder bumps on the bare chip and soldering to the interposer.